1. Field of the Invention
The present invention relates to a capacitor embedded in an interposer mounted immediately below a semiconductor integrated circuit element or the like, a semiconductor device including the same, and a method for manufacturing a capacitor embedded in an interposer.
2. Description of the Related Art
Along with the recent progress in CoC (Chip on Chip) technology, there has been proposed a technique for mounting a high-capacity memory chip and a logic chip on one semiconductor package substrate and implementing high-speed signal transmission between the memory chip and the logic chip. FIG. 9 is a schematic view showing a conventional semiconductor device.
In the conventional semiconductor device, for example, a multilayer wiring 109 is formed on a silicon substrate 101 to constitute an interposer. Semiconductor integrated circuit elements 122a and 122b including microscopic bumps (micro-bumps) are mounted on electrode pads on the multilayer wiring 109. One of the semiconductor integrated circuit elements 122a and 122b is a memory chip, and the other is a logic chip. An under-filling resin 126 is provided between the semiconductor integrated circuit elements 122a and 122b, and the multilayer wiring 109. A plurality of electrode pads for wires are also provided on the multilayer wiring 109, and wires 124, including a signal line, a power line, and a ground line, are connected to the electrode pads. The interposer is mounted on a package substrate (not shown), and the other ends of the wires 124 are connected to the package substrate. Since the semiconductor integrated circuit elements 122a and 122b are close to each other, this semiconductor device is capable of high-speed data transmission. The bit width increases with an increase in the number of microscopic bumps.
There has also been developed an interposer with embedded decoupling capacitors. If such an interposer is used, a decoupling capacitor is located immediately below a semiconductor integrated circuit element. Accordingly, the reduced length of a piece of wiring can be routed from a power supply terminal and a grounding terminal of the semiconductor integrated circuit element to the decoupling capacitor, and the inductance can be reduced (Japanese Patent Application Laid-Open Nos. 7-176453, 2001-68583, 2001-35990, and 2004-304159, hereinafter referred to as Patent Documents 1 to 4, respectively). There has further been proposed a technique for reducing the thickness of a capacitor insulating film in order to increase the capacitance of a decoupling capacitor (Japanese Patent Application Laid-Open Nos. 2003-197463, 2004-79801, and 2004-214589, hereinafter referred to as Patent Documents 5 to 7, respectively).
The semiconductor device shown in FIG. 9, however, needs the wires 124 to connect the interposer and the package substrate, and the speed at which a signal is transmitted through the wire 124 is not sufficient. Although studies are underway on a technique for forming a through via in a support substrate for an interposer, for example, the silicon substrate 101 and transmitting a signal between the interposer and a package substrate through the through via, such a technique is hard to implement. This is because the technique requires the process of forming through holes corresponding to microscopic bumps in the support substrate for the interposer at short intervals and filling each through hole with a conductor. Especially, in the techniques disclosed in Patent Documents 1 to 4, for example, a through via needs to be formed in a support substrate. It is thus necessary to form a through via by co-firing a conductor and ceramic or by forming a through hole in a silicon substrate, insulating inter-via portions, and then filling the hole with a conductor. These processes are extremely difficult and require significant cost.
In the techniques disclosed in Patent Documents 5 to 7, a noble metal material which is resistant to oxidation, such as Pt or Au, is required as the material for an electrode of a thin film capacitor. It is also necessary to introduce vacuum equipment such as a sputtering system intended to form a high dielectric film. Further, it needs to remove particles in order to improve yields of thin film capacitors. For these reasons, significant cost is required.
Large capacitances of decoupling capacitors are required to reduce noise in various semiconductor integrated circuit elements. This may have an assumption that a sufficient number of conventional multi-layered capacitors cannot mount on an interposer substrate in the future.